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a sharc and the sharc logo are registered trademarks of ana log devices, inc. sharc ? processor adsp-21362/ADSP-21363/adsp-2 1364/adsp-21365/adsp-21366 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel : 781.329.4700 www.analog.com fax: 781.461.3113 ? 2006 analog devices, inc. all rights reserved. summary high performance, 32-bit/40-bi t, floating-point processor optimized for high performance processing single-instruction, multiple-data (simd) computational architecture on-chip memory3m bit of on-chip sram code compatible with all other members of the sharc family the adsp-2136x processors are available with a 333 mhz core instruction rate and unique peripherals such as the digi- tal audio interface, s/pdif transceiver, dtcp (digital transmission content protection protocol), serial ports, 8-channel asynchronous samp le rate converter, precision clock generators, and more. for complete ordering informa- tion, see ordering guide on page 52 . figure 1. functional block diagramprocessor core addr data iod addr data ioa addr data ioa sram 1m bit rom 2m bit sram 0.5m bit block 0 block 1 block 2 block 3 addr data ioa iop registers (memory mapped) i/o processor and peripherals 6 jtag test and emulation 32 pm address bus dm address bus 32 pm data bus dm data bus 64 64 px register processing element (pey) processing element (pex) timer instruction cache 32-bit 48-bit dag1 8 4 32 dag2 8 4 32 core processor program sequencer sram 1m bit rom 2m bit signal routing unit sram 0.5m bit 4 blocks of on-chip memory iod ioa iod iod spi sports idp pcg timers src spdif dtcp s
rev. a | page 2 of 52 | december 2006 adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 key featuresprocessor core at 333 mhz (3.0 ns) core instruction rate, the adsp-2136x performs 2 gflops/666 mmacs 3m bit on-chip sram (1m bit in blocks 0 and 1, and 0.50m bit in blocks 2 and 3) for simultaneous access by the core pro- cessor and dma 4m bit on-chip rom (2m bit in block 0 and 2m bit in block 1) dual data address generators (dags) with modulo and bit- reverse addressing zero-overhead looping with single-cycle loop setup, provid- ing efficient program sequencing single-instruction multiple-data (simd) architecture provides: two computational processing elements concurrent execution code compatibility with othe r sharc family members at the assembly level parallelism in buses and computational units allows single cycle execution (with or wi thout simd) of a multiply operation, an alu operation, a dual memory read or write, and an instruction fetch transfers between memory and core at a sustained 5.4g bytes/s bandwidth at 333 mhz core instruction rate input/output features dma controller supports: 25 dma channels for transfers between adsp-2136x internal memory and a variety of peripherals 32-bit dma transfers at peripheral clock speed, in parallel with full-speed processor execution asynchronous parallel port provides access to asynchronous external memory 16 multiplexed address/data lines support 24-bit address external address range with 8-bit data or 16-bit address external address range with 16-bit data 55m byte per sec transfer rate external memory access in a dedicated dma channel 8-bit to 32-bit and 16-bit to 32-bit packing options programmable data cycle duration: 2 cclk to 31 cclk digital audio interface (dai) includes six serial ports, two pre- cision clock generators, an input data port, three timers, an s/pdif transceiver, a dtcp cipher, an 8-channel asynchro- nous sample rate converte r, an spi port, and a signal routing unit six dual data line serial ports that operate at up to 41.67m bits/s on each data lineeach has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair left-justified sample pair and i 2 s support, programmable direction for up to 24 simultaneous receive or transmit channels using two i 2 s-compatible stereo devices per serial port tdm support for telecommunications interfaces including 128 tdm channel support for newer telephony interfaces such as h.100/h.110 up to 12 tdm stream support, each with 128 channels per frame companding selection on a per channel basis in tdm mode input data port provides an additional input path to the pro- cessor core, configurable as eight channels of serial data or seven channels of serial data, and up to a 20-bit wide paral- lel data channel signal routing unit provides configurable and flexible con- nections between all dai compon entsCsix serial ports, one spi port, eight channels of as ynchronous sample rate con- verters, an s/pdif receiver/transmitter, three timers, an spi port,10 interrupts, six flag inputs, six flag outputs, and 20 sru i/o pins (dai_px) two serial peripheral interfaces (spi): primary on dedicated pins, secondary on dai pins provide: master or slave serial boot through primary spi full-duplex operation master slave mode multimaster support open drain outputs programmable baud rates, clock polarities, and phases 3 muxed flag/irq lines 1 muxed flag/timer expired line dedicated audio components s/pdif-compatible digital au dio receiver/transmitter supports: eiaj cp-340 (cp-1201), iec-958, aes/ebu standards left-justified, i 2 s, or right-justified serial data input with 16-, 18-, 20- or 24-bit word widths (transmitter) two channel mode and single channel double frequency (scdf) mode sample rate converter (src) contains a serial input port, de-emphasis filter, sample rate converter (src) and serial output port providing up to C140 db snr performance (see table 2 on page 4 ) supports left-justified, i 2 s, tdm, and right-justified 24-, 20-, 18-, and 16-bit serial formats (input) pulse-width modulation provides: 16 pwm outputs configured as four groups of four outputs supports center-aligned or edge-aligned pwm waveforms can generate complementary signals on two outputs in paired mode or independen t signals in nonpaired mode rom-based security features include: jtag access to memory permitted with a 64-bit key protected memory regions that can be assigned to limit access under program cont rol to sensitive code pll has a wide variety of software and hardware multi- plier/divider ratios dual voltage: 3.3 v i/o, 1.2 v core available in 136-ball bga package (see ordering guide on page 52 )
adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 rev. a | page 3 of 52 | december 2006 table of contents summary ................................................................1 key featuresprocessor core ..................................2 input/output features ............................................2 dedicated audio components ..................................2 general description ..................................................4 sharc family core architecture .............................5 memory and i/o interface features ............................6 development tools .............................................. 10 additional information ......................................... 11 pin function descriptions ........................................ 12 address data pins as flags .................................. 15 address/data modes ............................................ 15 boot modes ........................................................ 15 core instruction rate to clkin ratio modes ............. 15 adsp-2136x specifications ....................................... 16 operating conditions ........................................... 16 electrical characteristics ........................................ 16 package information ............................................ 17 maximum power dissipation ................................. 17 absolute maximum ratings ................................... 17 esd sensitivity .................................................... 17 timing specifications ........................................... 18 output drive currents .......................................... 46 test conditions ................................................... 46 capacitive loading ............................................... 46 thermal characteristics ........................................ 47 136-ball bga pin configurations .. ............................. 48 outline dimensions ................................................ 51 surface mount design .......................................... 51 ordering guide ...................................................... 52 revision history 12/06rev 0 to rev a this version of the data sh eet combines the adsp-21362, ADSP-21363, adsp-21364, adsp-21365, and adsp-21366 data sheets. throughout this document, these products are referred to as adsp-2136x except where features or specifica- tions apply to a specific proce ssor. for a comparison of each processor, see table 2 on page 4 . added package information ......................................17 fixed figure 6 , core clock and system clock relationship to clkin .................................................................18 fixed figure 24 , idp master timing ............................34 this version of the data sheet is for bga parts only. an alternate lqfp package (exposed pad) wi ll be available in the future. information on that option is available on the adsp-21365 product page. see ordering guide ...............................52
rev. a | page 4 of 52 | december 2006 adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 general description the adsp-2136x sharc processor is a member of the simd sharc family of dsps that feat ure analog devices super har- vard architecture. the processo r is source code-compatible with the adsp-2126x and adsp-2 116x dsps, as well as with first generation adsp-2106x shar c processors in sisd (sin- gle-instruction, single-data) mode. the adsp-2136x is a 32-bit/40-bit floating-point pr ocessor optimized for high performance automotive audio applications with a large on- chip sram and rom, multiple internal buses to eliminate i/o bottlenecks, and an innovative digital audio interface (dai). as shown in the functional block diagram on page 1 , the adsp-2136x uses two computationa l units to deliver a signifi- cant performance increase over the previous sharc processors on a range of signal processing algorithms. fabricated in a state- of-the-art, high speed, cmos process, the adsp-2136x proces- sor achieves an instruction cycle time of 3.0 ns at 333 mhz. with its simd computational hardware, the adsp-2136x can perform two gflops running at 333 mhz. table 2 shows the features of the individual product offerings and table 1 shows performance benchmarks for the processors running at 333 mhz. the adsp-2136x continues shar cs industry-l eading stan- dards of integration for dsps, combining a high performance 32-bit dsp core with integrated, on-chip system features. the block diagram on page 1 , illustrates the following architec- tural features: ? two processing elements, each of which comprises an alu, multiplier, shifter, and data register file ? data address generators (dag1, dag2) ? program sequencer with instruction cache ? pm and dm buses capable of supporting four 32-bit data transfers between me mory and the core at every core pro- cessor cycle ? three programmable interval timers with pwm genera- tion, pwm capture/pulse width measurement, and external event counter capabilities ?on-chip sram (3m bit) ? on-chip rom (4m bit) ? 8-bit or 16-bit parallel port th at supports interfaces to off- chip memory peripherals ? jtag test access port the block diagram on page 7 illustrates the following architec- tural features: ? dma controller ? six full duplex serial ports ? two spi-compatible interface portsprimary on dedi- cated pins, secondary on dai pins ? digital audio interface that includes two precision clock generators (pcg), an input da ta port (idp), an s/pdif receiver/transmitter, eight ch annels asynchronous sample rate converter, dtcp cipher, si x serial ports, eight serial interfaces, a 20-bit parallel input port, 10 interrupts, six flag outputs, six flag inputs, three timers, and a flexible signal routing unit (sru) figure 2 shows a sample sport conf iguration using the preci- sion clock generators to interface with an i 2 s adc and an i 2 s dac with a much lower jitter clock than the serial port would generate itself. many other sru configurations are possible. table 1. benchmarks (at 333 mhz) benchmark algorithm speed (at 333 mhz) 1024 point complex fft (radix 4, with reversal) 27.9 s fir filter (per tap) 1 1 assumes two files in multichannel simd mode 1.5 ns iir filter (per biquad) 1 6.0 ns matrix multiply (pipelined) [33] [31] [44] [41] 13.5 ns 23.9 ns divide (y/x) 10.5 ns inverse square root 16.3 ns table 2. adsp-2136x sharc processor family features feature adsp-21362 ADSP-21363 adsp-21364 adsp-21365 adsp-21366 ram 3m bit 3m bit 3m bit 3m bit 3m bit rom 4m bit 4m bit 4m bit 4m bit 4m bit audio decoders in rom 1 1 audio decoding algorithms include pcm, dolby digital ex, dolby prologic iix, dts 96/24, neo:6, dts es, mpeg-2 aac, mp3, and functions like bass management, delay, speake r equalization, graphic equalization, and more. decoder/post-processor algorithm combin ation support varies depending upon the chip version and the system configura tions. please visit www.analog.com for complete information. no no no yes yes pulse width modulation yes yes yes yes yes s/pdif yes no yes yes yes dtcp 2 2 the adsp-21362 and adsp-2 1365 processors provide the digital transmission content protection protoc ol, a proprietary security protocol. contact your analog devices sales office for more information. yes no no yes no src performance 128 db no src 140 db 128 db 128 db
adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 rev. a | page 5 of 52 | december 2006 sharc family core architecture the adsp-2136x is code-compatibl e at the assembly level with the adsp-2126x, adsp-21160, an d adsp-21161, and with the first generation adsp-2106x sharc processors. the adsp-2136x shares architectural features with the adsp-2126x and adsp-2116x simd sharc proc essors, as detailed in the following sections. simd computational engine the adsp-2136x contai ns two computational processing ele- ments that operate as a single-instruction multiple-data (simd) engine. the processing elements are referred to as pex and pey and each contains an alu, multiplier, shifter, and register file. pex is always active, and pey may be enabled by setting the peyen mode bit in the mode1 register. when this mode is enabled, the same instruction is executed in both processing ele- ments, but each processing elem ent operates on different data. this architecture is efficient at executing math intensive signal processing algorithms. entering simd mode also has an effect on the way data is trans- ferred between memory and the processing elements. when in simd mode, twice the data bandwidth is required to sustain computational operation in the processing elements. because of this requirement, entering simd mode also doubles the bandwidth between memory an d the processing elements. when using the dags to transfer data in simd mode, two data values are transferred with each access of memory or the regis- ter file. independent, parallel computation units within each processing element is a set of computational units. the computational units consist of an arithmetic/logic unit (alu), multiplier, and shifter. these units perform all opera- tions in a single cycl e. the three units within each processing element are arranged in paralle l, maximizing computational throughput. single multifunctio n instructions execute parallel alu and multiplier operations . in simd mode, the parallel alu and multiplier operations occur in both processing elements. these computatio n units support ieee 32-bit single-precision floating-point, 40-bit extended-precision floating-point, and 32-bit fixed-point data formats. data register file a general-purpose data register file is contained in each pro- cessing element. the register files transfer data between the computation units and the data buses, and store intermediate results. these 10-port, 32-regist er (16 primary, 16 secondary) register files, combined wi th the adsp-2136x enhanced figure 2. adsp-2136x system sample configuration dai spi id p src spdif sp ort0-5 sclk0 sd0a sfs0 sd0b sru dai_p1 da i_ p2 da i_ p3 dai_p18 dai_p19 da i_ p2 0 dac (optional) adc (optional) fs clk sdat fs clk sdat 3 clock flag3-1 2 2 clkin xtal clk_cfg1-0 bootcfg1-0 addr parallel port ram i/o device oe data we rd wr clkout ale ad 1 5- 0 latch reset jta g 6 adsp-2136x a d d r e s s d a t a c o n t r o l cs flag0 pcgb pcga clk fs timers
rev. a | page 6 of 52 | december 2006 adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 harvard architecture, allow unconstrained data flow between computation units and internal memory. the registers in pex are referred to as r0 C r15 and in pey as s0 C s15. single-cycle fetch of instruction and four operands the adsp-2136x features an enha nced harvard architecture in which the data memory (dm) bu s transfers data and the pro- gram memory (pm) bus transfer s both instructions and data (see figure 1 on page 1 ). with the processors separate program and data memory buses and on-c hip instruction cache, the pro- cessor can simultaneously fetch fo ur operands (two over each data bus) and one instructio n (from the cache), all in a single cycle. instruction cache the adsp-2136x includes an on -chip instruction cache that enables three-bus operat ion for fetching an instruction and four data values. the cache is select iveonly the instructions whose fetches conflict with pm bus data accesses are cached. this cache allows full-speed executio n of core, looped operations such as digital filter multiply -accumulates, and fft butterfly processing. data address generators with zero-overhead hardware circular buffer support the adsp-2136xs two data addr ess generators (dags) are used for indirect addressing and implementing circular data buffers in hardware. circular buffers allow efficient program- ming of delay lines and other data structures required in digital signal processing, and are common ly used in digi tal filters and fourier transforms. the two dags contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). th e dags automatically handle address pointer wraparound, redu ce overhead, increase perfor- mance, and simplify implementation. circular buffers can start and end at any memory location. flexible instruction set the 48-bit instruction word accommodates a variety of parallel operations, for concise prog ramming. for example, the adsp-2136x can conditio nally execute a multip ly, an add, and a subtract in both processing elements while branching and fetch- ing up to four 32-bit values from memoryall in a single instruction. memory and i/o interface features the adsp-2136x adds the following architectural features to the simd sharc family core. on-chip memory the adsp-2136x contains three megabits of internal sram and four megabits of internal rom. each block can be config- ured for different combinations of code and data storage (see table 3 ). each memory block supports single-cycle, indepen- dent accesses by the core proc essor and i/o processor. the processors memory architecture, in combination with its sepa- rate on-chip buses, allows two data transfers from the core and one from the i/o processo r, in a single cycle. table 3. adsp-2136x internal memory space iop registers 0x0000 0000C0003 ffff long word (64 bits) extended precision normal or instruction word (48 bits) normal word (32 bits) short word (16 bits) block 0 rom 0x0004 0000C0x0004 7fff block 0 rom 0x0008 0000C0x0008 aaa9 block 0 rom 0x0008 0000C0x0008 ffff block 0 rom 0x0010 0000C0x0011 ffff reserved 0x0004 8000C0x0004 bfff reserved 0x0009 0000C0x0009 7fff reserved 0x0012 0000C0x0012 ffff block 0 sram 0x0004 c000C0x0004 ffff block 0 sram 0x0009 0000C0x0009 5554 block 0 sram 0x0009 8000C0x0009 ffff block 0 sram 0x0013 0000C0x0013 ffff block 1 rom 0x0005 0000C0x0005 7fff block 1 rom 0x000a 0000C0x000a aaa9 block 1 rom 0x000a 0000C0x000a ffff block 1 rom 0x0014 0000C0x0015 ffff reserved 0x0005 8000C0x0005 bfff reserved 0x000b 0000C0x000b 7fff reserved 0x0016 0000C0x0016 ffff block 1 sram 0x0005 c000C0x0005 ffff block 1 sram 0x000b 0000C0x000b 5554 block 1 sram 0x000b 8000C0x000b ffff block 1 sram 0x0017 0000C0x0017 ffff block 2 sram 0x0006 0000C0x0006 1fff block 2 sram 0x000c 0000C0x000c 2aa9 block 2 sram 0x000c 0000C0x000c 3fff block 2 sram 0x0018 0000C0x0018 7fff reserved 0x0006 2000C0x0006 ffff reserved 0x000c 4000C0x000d ffff reserved 0x0018 8000C0x001b ffff block 3 sram 0x0007 0000C0x0007 1fff block 3 sram 0x000e 0000C0x000e 2aa9 block 3 sram 0x000e 0000C0x000e 3fff block 3 sram 0x001c 0000C0x001c 7fff
adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 rev. a | page 7 of 52 | december 2006 the sram can be configured as a maximum of 96k words of 32-bit data, 192k words of 16- bit data, 64k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to three megabits. all of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. a 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on -chip. conversion between the 32- bit floating-point and 16-bit floating-point formats is per- formed in a single instruction. while each memory block can store combinations of code and data, accesses are most efficient when one block stores data usin g the dm bus for transfers, and the other block stores instructions and data using the pm bus for transfers. using the dm bus and pm buses, with one bus dedicated to each memory block, assures si ngle-cycle execution with two data transfers. in this case, the instruction must be available in the cache. dma controller the adsp-2136xs on-chip dma co ntrollers allow data trans- fers without processor inte rvention. the dma controller operates independently and invi sibly to the processor core, allowing dma operations to oc cur while the core is simulta- neously executing its program in structions. dma transfers can occur between the processors in ternal memory and its serial ports, the spi-compatible (serial peripheral interface) ports, the idp (input data port), the parallel data acquisition port (pdap), or the parallel port. twenty-five channels of dma are available on the processorstwo for the sp i interface, 12 via the serial ports, eight via the input data port, two for dtcp (or memory- to-memory data transfer when dt cp is not used), and one via the processors parallel port. pr ograms can be downloaded to the processors using dma tran sfers. other dma features include interrupt generation upon completion of dma trans- fers, and dma chaining for automatic linked dma transfers. digital audio interface (dai) the digital audio interface (dai) provides the ability to connect various peripherals to any of the dsps dai pins (dai_p20C1). programs make these connections using the signal routing unit (sru, shown in figure 3 ). the sru is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the dai to be intercon- nected under software control. this allows easy use of the dai- associated peripherals for a much wider variety of applica- tions by using a larger set of al gorithms than is possible with nonconfigurable signal paths. the dai also includes six serial ports, an s/pdif receiver/trans- mitter, a dtcp cipher, a precisio n clock generator (pcg), eight channels of asynchronous sample rate converters, an input data port (idp), an spi port, six flag outputs and six flag inputs, and reserved 0x0007 2000C0x0007 ffff reserved 0x000e 4000C0x000f ffff reserved 0x001c 8000C0x001f ffff reserved 0x0020 0000C0xffff ffff table 3. adsp-2136x internal memory space (continued) iop registers 0x0000 0000C0003 ffff long word (64 bits) extended precision normal or instruction word (48 bits) normal word (32 bits) short word (16 bits) figure 3. adsp-2136x i/o processor and peripherals block diagram 16 3 precision clock generators (2) spi port (1) 4 serial ports (6) input data ports (8) timers (3) 3 dma controller i o p r e g i s t e r s ( m e m o r y m a p p e d ) c o n t r o l , s t a t u s , a n d d a t a b u f f e r s parallel port 4 gpio flags/irq/timexp s i g n a l r o u t i n g u n i t address/data bus/ gpio control/gpio digital audio interface 25 channels to processor buses and system memory io address bus (18) src (8 channels) spdif (rx/tx) dtcp cipher pwm (16) io data bus (32) spi port (1) 4 20 i/o processor
rev. a | page 8 of 52 | december 2006 adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 three timers. the idp provides an additional input path to the adsp-2136x core, configurable as either eight channels of i 2 s serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisitio n port. each data channel has its own dma channel that is independent from the processors serial ports. for complete information on using the dai, see the adsp-2136x sharc proce ssor hardware reference . serial ports the adsp-2136x features six sync hronous serial ports that pro- vide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as analog devices ad183x family of audio codecs , adcs, and dacs. the serial ports are made up of two data lines, a clock, and a frame sync. the data lines can be programmed to either transmit or receive and each data line has a dedicated dma channel. serial ports are enabled via 12 programmable and simultaneous receive or transmit pins that support up to 24 transmit or 24 receive channels of audio data when all six sports are enabled, or six full duplex tdm stream s of 128 channels per frame. the serial ports operate at a maximum data rate of 41.67 m bits/s. serial port data can be automatically transferred to and from on-chip memory via dedicated dma channels. each of the serial ports can work in conjunct ion with another serial port to provide tdm support. one sport provides two transmit sig- nals while the other sport provides the two receive signals. the frame sync and clock are shared. serial ports operate in four modes: ? standard dsp serial mode ? multichannel (tdm) mode ?i 2 s mode ? left-justified sample pair mode left-justified sample pair mode is a mode where in each frame sync cycle two samples of data are transmitte d/receivedone sample on the high segment of the frame sync, the other on the low segment of the frame sync. programs have control over var- ious attributes of this mode. each of the serial ports supports the left-justified sample pair and i 2 s protocols (i 2 s is an industry-standard interface com- monly used by audio codecs, adcs, and dacs, such as the analog devices ad183x family), with two data pins, allowing four left-justified sample pair or i 2 s channels (using two stereo devices) per serial port, with a maximum of up to 24 i 2 s chan- nels. the serial ports permit little-endian or big-endian transmission formats an d word lengths selectab le from 3 bits to 32 bits. for the left-justified sample pair and i 2 s modes, data- word lengths are selectable between 8 bits and 32 bits. serial ports offer selectable synchron ization and transmit modes as well as optional -law or a-law companding selection on a per channel basis. serial port clocks and frame syncs can be inter- nally or extern ally generated. parallel port the parallel port provides interf aces to sram and peripheral devices. the multiplexed address and data pins (ad15C0) can access 8-bit devices with up to 24 bits of address, or 16-bit devices with up to 16 bits of ad dress. in either mode, 8-bit or 16-bit, the maximum data transfer rate is 55m bytes/sec. dma transfers are used to move data to and from internal memory. access to the core is also facilitated through the paral- lel port register read/write functions. the rd , wr , and ale (address latch enable) pins ar e the control pins for the parallel port. serial peripheral (compatible) interface the processors contain two serial peripheral interface ports (spis). the spi is an industry-s tandard synchronous serial link, enabling the adsp-2136x spi-compatible po rt to communicate with other spi-compatible devices. the spi consists of two data pins, one device select pin, and one clock pin. it is a full-duplex synchronous serial interface, su pporting both master and slave modes. the spi port can operat e in a multimaster environment by interfacing with up to four other spi-compatible devices, either acting as a master or slave device. the adsp-2136x spi- compatible peripheral implemen tation also features program- mable baud rate, clock phase, and polarities. the spi- compatible port uses open drai n drivers to support a multimas- ter configuration and to avoid data contention. s/pdif-compatible digital audio receiver/transmitter and synchronous/asynchronous sample rate converter the s/pdif transmitter has no separate dma channels. it receives audio data in serial format and converts it into a biphase encoded signal. the serial data input to the transmitter can be formatted as left-justified, i 2 s, or right-justified with word widths of 16, 18, 20, or 24 bits. the serial data, clock, and fram e sync inputs to the s/pdif transmitter are routed through th e signal routing unit (sru). they can come from a variety of sources such as the sports, external pins, the precision clock generators (pcgs), or the sample rate converters (src) and are controlled by the sru control registers. the sample rate converter (src) contains four src blocks and is the same core as that us ed in the ad1896 192 khz stereo asynchronous sample rate conver ter and provides up to 140 db snr (see table 2 on page 4 for details). the src block is used to perform synchronous or asyn chronous sample rate conver- sion across independent stereo channels, without using internal processor resources. the four sr c blocks can also be config- ured to operate together to convert multichannel audio data without phase mismatches. finally, the src is used to clean up audio data from jittery clock sources such as the s/pdif receiver. the s/pdif and sr c are not available on the ADSP-21363 models. digital transmission content protection the dtcp specification defines a cryptographic protocol for protecting audio entertainment content from illegal copying, intercepting, and tampering as it traverses high performance
adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 rev. a | page 9 of 52 | december 2006 digital buses, such as the ieee 1394 standard . only legitimate entertainment content delivered to a source device via another approved copy protection syst em (such as the dvd content scrambling system) will be protec ted by this copy protection system. this feature is av ailable on the adsp-21362 and adsp-21365 processors only. licensing through dtla is required for these products. visit www.dtcp.com for more information. pulse-width modulation the pwm module is a flexible , programmable, pwm waveform generator that can be programmed to generate the required switching patterns for various a pplications related to motor and engine control or audio power control. the pwm generator can generate either center-aligned or edge-align ed pwm wave- forms. in addition, it can gene rate complementary signals on two outputs in paired mode or independent signals in non- paired mode (applicable to a single group of four pwm waveforms). the entire pwm module has four groups of four pwm outputs each. therefore, this module generates 16 pwm outputs in total. each pwm group produces two pairs of pwm signals on the four pwm outputs. the pwm generator is capable of operating in two distinct modes while generating center-aligned pwm waveforms: single update mode or double update mode. in single update mode the duty cycle values are programmab le only once per pwm period. this results in pwm patterns that are symmetrical about the midpoint of the pwm period. in double update mode, a second updating of the pwm registers is implemented at the midpoint of the pwm period. in this mo de, it is possible to produce asymmetrical pwm patterns that produce lower harmonic dis- tortion in three-ph ase pwm inverters. timers the adsp-2136x has a total of four timers: a core timer that can generate periodic software inte rrupts and three general-purpose timers that can generate periodic interrupts and be indepen- dently set to operate in one of three modes: ? pulse waveform generation mode ? pulse width count/capture mode ? external event watchdog mode the core timer can be configur ed to use flag3 as a timer expired signal, and each genera l-purpose timer has one bidirec- tional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32- bit pulse width register. a sin- gle control and status register enables or disables all three general-purpose timers independently. rom-based security the adsp-2136x has a rom securi ty feature that provides hardware support for securing user software code by preventing unauthorized reading from the internal code when enabled. when using this feature, the pr ocessor does not boot-load any external code, executing exclus ively from internal sram/rom. additionally, the processor is no t freely accessible via the jtag port. instead, a unique 64-bit ke y, which must be scanned in through the jtag or test access port will be assigned to each customer. the device will ignore a wrong key. emulation fea- tures and external boot modes are only available after the correct key is scanned. program booting the internal memory of the adsp-2136x boots at system power-up from an 8-bit eprom via the parallel port, an spi master, an spi slave, or an inte rnal boot. booting is determined by the boot configuration (bootcfg1C0) pins (see table 7 on page 15 ). selection of the boot source is controlled via the spi as either a master or slave device, or it can immediately begin exe- cuting from rom. phase-locked loop the processors use an on-chip ph ase-locked loop (pll) to gen- erate the internal clock for the core. on power up, the clkcfg1C0 pins are used to select ratios of 32:1, 16:1, and 6:1 (see table 8 on page 15 ). after booting, numerous other ratios can be selected vi a software control. the ratios are made up of soft ware configurable numerator val- ues from 1 to 64 and software conf igurable divisor values of 1, 2, 4, and 8. power supplies the adsp-2136x has a separate power supply connection for the internal (v ddint ), external (v ddext ), and analog (a vdd /a vss ) power supplies. the internal and analog supplies must meet the 1.2 v requirement for k, b, an d y grade models, and the 1.0 v requirement for y and w grade models. (for information on the temperature ranges offe red for this product, see operating conditions on page 16 , package information on page 17 , and ordering guide on page 52 . the external supply must meet the 3.3 v requirement. all external supply pins must be connected to the same power supply. note that the analog supply pin (a vdd ) powers the processors internal clock generator pll. to produce a stable clock, it is rec- ommended that pcb designs use an external filter circuit for the a vdd pin. place the filter components as close as possible to the a vdd /a vss pins. for an example circuit, see figure 4 . (a recom- mended ferrite chip is the murata blm18ag102sn1d). to reduce noise coupling, the pcb should use a parallel pair of power and ground planes for v ddint and gnd. use wide traces to connect the bypass capacitors to the analog power (a vdd ) and ground (a vss ) pins. note that the a vdd and a vss pins specified in figure 4 are inputs to the processo r and not the analog ground plane on the boardthe a vss pin should connect directly to dig- ital ground (gnd) at the chip. target board jtag emulator connector analog devices dsp tools product line of jtag emulators uses the ieee 1149.1 jtag test access po rt of the processor to moni- tor and control the target boar d processor during emulation. analog devices dsp tools product line of jtag emulators provides emulation at full proce ssor speed, allowi ng inspection
rev. a | page 10 of 52 | december 2006 adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 and modification of memory, re gisters, and processor stacks. the processors jtag interface ensures that the emulator will not affect target system loading or timing. for complete information on analog devices sharc dsp tools product line of jtag emulator operation, see the appro- priate emulator hardware users guide. development tools the adsp-2136x is supported with a complete set of crosscore ? ? software and hardware development tools, including analog devices emulators and visualdsp++ ? ? devel- opment environment. the same emulator hardware that supports other sharc processors also fully emulates the adsp-2136x. the visualdsp++ project management environment lets pro- grammers develop and debug an application. this environment includes an easy to use assembler (which is based on an alge- braic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accura te instruction-level simulator, a c/c++ compiler, and a c/c++ runtime library that includes dsp and mathematical functions. a key point for these tools is c/c++ code efficiency. the compiler ha s been developed for efficient translation of c/c++ code to dsp assembly. the sharc has architectural features that impr ove the efficiency of compiled c/c++ code. the visualdsp++ debugger has a number of important fea- tures. data visualization is enhanced by a plotting package that offers a significant level of flexibility. this graphical representa- tion of user data enables the programmer to quickly determine the performance of an algorithm. as algorithms grow in com- plexity, this capability can have increasing significance on the designers development schedule, increasing productivity. sta- tistical profiling enables the pr ogrammer to nonintrusively poll the processor as it is running the program. this feature, unique to visualdsp++, enables the software developer to passively gather important code executio n metrics without interrupting the real-time characteristics of the program. essentially, the developer can identify bottlenecks in software quickly and efficiently. by using the profil er, the programmer can focus on those areas in the program that impact performance and take corrective action. debugging both c/c++ and assembly programs with the visualdsp++ debugger, programmers can: ? view mixed c/c++ and assembly code (interleaved source and object information) ? insert breakpoints ? set conditional breakpoints on registers, memory, and stacks ? trace instruction execution ? perform linear or statistical profiling of program execution ? fill, dump, and graphically plot the contents of memory ? perform source level debugging ? create custom debugger windows the visualdsp++ idde lets programmers define and manage dsp software development. its di alog boxes and property pages let programmers configure and manage all of the sharc devel- opment tools, including the colo r syntax highlighting in the visualdsp++ editor. this capability permits programmers to: ? control how the development tools process inputs and generate outputs ? maintain a one-to-one correspondence with the tools command line switches the visualdsp++ kernel (vdk) incorporates scheduling and resource management tailored sp ecifically to address the mem- ory and timing constraints of dsp programming. these capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. the vdk features include threads, critical and unschedule d regions, semaphores, events, and device flags. the vdk also supports priority-based, pre- emptive, cooperative, and time-s liced scheduling approaches. in addition, the vdk was designed to be scalable. if the application does not use a specific feature, the support code for that feature is excluded from the target system. because the vdk is a library, a developer can decide whether to use it or not. the vdk is integrated into the visualdsp++ development environment, but ca n also be used via standard command line tools. when the vdk is used, the development environment assists th e developer with many error-prone tasks and assists in managi ng system resources, automating the gen- eration of various vdk-based objects, and vi sualizing the system state, when debugging an application that uses the vdk. visualdsp++ component software engineering (vcse) is ana- log devices technology for creati ng, using, and reusing software components (independent modules of substantial functionality) to quickly and reliably assemble software applications. it allows downloading components from th e web, dropping them into the application, and publishing component archives from within visualdsp++. vcse su pports component implementa- tion in c/c++ or assembly language. use the expert linker to visually manipulate the placement of code and data on the embedded system. view memory utiliza- tion in a color-coded graphical form, easily move code and data to different areas of the processor or external memory with a figure 4. analog power (a vdd ) filter circuit ? crosscore is a registered trademark of analog devices, inc. ? visualdsp++ is a registered trademark of analog devices, inc. hi z ferrite bead chip locate all components close to a vdd and a vss pins a vdd a vss 100nf 10nf 1nf adsp-213xx v ddint
adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 rev. a | page 11 of 52 | december 2006 drag of the mouse and examine runtime stack and heap usage. the expert linker is fully compatible with the existing linker def- inition file (ldf), allowing the developer to move between the graphical and textual environments. in addition to the software and hardware development tools available from analog devices, third parties provide a wide range of tools supporting the sharc processor family. hard- ware tools include sharc proce ssor pc plug-in cards. third party software tools include dsp libraries, real-time operating systems, and block diagram design tools. designing an emulator-compatible dsp board (target) the analog devices family of emulators are tools that every dsp developer needs to test an d debug hardware and software systems. analog devices has supp lied an ieee 1149.1 jtag test access port (tap) on each jtag processor. nonintrusive in- circuit emulation is assured by the use of the processors jtag interfacethe emulator does not af fect target system loading or timing. the emulator uses the tap to access the internal fea- tures of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. the processor must be halted to send data and com- mands, but once an operation has been completed by the emulator, the dsp system is set running at full speed with no impact on system timing. to use these emulators, the targ et board must include a header that connects the dsps jtag port to the emulator. for details on target board desi gn issues including mechanical layout, single processor conn ections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the ee-68: analog devices jt ag emulation technical reference on the analog devices website ( www.analog.com ) use site search on ee-68. this document is updated regularly to keep pace with improvem ents to emulator support. evaluation kit analog devices offers a range of ez-kit lite ? ? evaluation plat- forms to use as a cost-effective method to learn more about developing or prototyping appl ications with analog devices processors, platforms, and softwa re tools. each ez-kit lite platform includes an evaluation board along with an evaluation suite of the visualdsp++ development and debugging environ- ment with the c/c++ compiler, assembler, and linker. also included are sample applicatio n programs, power supply, and a usb cable. all evaluation versions of the software tools are lim- ited for use only with the ez-kit lite product. the usb controller on the ez-k it lite board connects the board to the usb port of th e users pc, enabling the visualdsp++ evaluation suite to emulate the on-board proces- sor in-circuit. this permits the customer to download, execute, and debug programs for the ez-kit lite system. it also allows in-circuit programming of the on-board flash device to store user-specific boot co de, enabling the board to run as a stand- alone unit without being connected to the pc. with a full version of visualdsp ++ installed (sold separately), engineers can develop software fo r the ez-kit lite or any cus- tom defined system. connecting one of analog devices jtag emulators to the ez-kit lite board enables high speed, non- intrusive emulation. additional information this data sheet provides a general overview of the adsp-2136x architecture and func tionality. for detailed infor- mation on the adsp-2136x fa mily core architecture and instruction set, refer to the adsp-2136x sharc processor hardware reference and the adsp-2136x sharc processor programming reference . ? ez-kit lite is a registered trademark of analog devices, inc.
rev. a | page 12 of 52 | december 2006 adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 pin function descriptions the adsp-2136x pin defi nitions are listed be low. inputs identi- fied as synchronous (s) must m eet timing requirements with respect to clkin (or with respect to tck for tms and tdi). inputs identified as asynchronous (a) can be asserted asynchro- nously to clkin (or to tck for trst ). tie or pull unused inputs to v ddext or gnd, except for the following: ? dai_px, spiclk, miso, mosi, emu , tms, trst , tdi, and ad15C0 (note: these pins have pull-up resistors.) the following symbol s appear in the type column of table 4 : a = asynchronous, g = ground, i = input, o = output, p = power supply, s = synchronous, (a/d) = active drive, (o/d) = open drain, and t = three-state, (pd) = pull-down resis- tor, (pu) = pull-up resistor. table 4. pin descriptions pin type state during and after reset description ad15C0 i/o/t (pu) three-state with pull-up enabled parallel port address/data. the adsp-2136x parallel port and its corresponding dma unit output addresses and data for pe ripherals on these multiplexed pins. the multiplex state is determined by the ale pi n. the parallel port can operate in either 8-bit or 16-bit mode. each ad pin has a 22.5 k internal pull-up resistor. see address/data modes on page 15 for details of the ad pin operation. for 8-bit mode: ale is automatically asserted whenever a change occurs in the upper 16 external address bits, a23C 8; ale is used in conjunctio n with an external latch to retain the values of the a23C8. for detailed information on i/o operations and pin multiplexing, see the adsp-2136x sharc processor hardware reference . rd o (pu) three-state, driven high 1 parallel port read enable. rd is asserted low whenever the processor reads 8-bit or 16-bit data from an external memory device. when ad15C0 are flags, this pin remains deasserted. rd has a 22.5 k internal pull-up resistor. wr o (pu) three-state, driven high 1 parallel port write enable. wr is asserted low whenever the processor writes 8-bit or 16-bit data to an external memory device. when ad15C0 are flags, this pin remains deasserted. wr has a 22.5 k internal pull-up resistor. ale o (pd) three-state, driven low 1 parallel port address latch enable. ale is asserted whenever the processor drives a new address on the parallel port address pins . on reset, ale is active high. however, it can be reconfigured using software to be active low. when ad15C0 are flags, this pin remains deasserted. ale has a 20 k internal pull-down resistor. flag3C0 i/o/a three-state flag pins. each flag pin is configured via control bits as either an input or output. as an input, it can be tested as a condition. as an output, it can be used to signal external peripherals. these pins can be used as an spi interface slave select output during spi mastering. these pins are also multiplexed with the irqx and the timexp signals. for detailed information on i/o operations and pin multiplexing, see the adsp-2136x sharc processor hardware reference . dai_p20C1 i/o/t (pu) three-state with programmable pull-up digital audio interface pins . these pins provide the physical interface to the sru. the sru configuration registers define the combination of on-chip peripheral inputs or outputs connected to the pin and to th e pins output enable. the configuration registers of these peripherals then determines the exact behavior of the pin. any input or output signal present in the sru may be routed to any of these pins. the sru provides the connection from the serial ports, input data port, precision clock gener- ators and timers, sample rate converters and spi to the dai_p20C1 pins. these pins have internal 22.5 k pull-up resistors which are enabled on reset. these pull-ups can be disabled in the dai_pin_pullup register.
adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 rev. a | page 13 of 52 | december 2006 spiclk i/o (pu) three-state with pull-up enabled serial peripheral interface clock signal . driven by the master, this signal controls the rate at which data is transferred. the ma ster may transmit data at a variety of baud rates. spiclk cycles once for each bit transmitted. spiclk is a gated clock that is active during data transfers, only for the length of the transferred word. slave devices ignore the serial clock if the slave select input is dr iven inactive (high). sp iclk is used to shift out and shift in the data driven on the miso and mosi lines. the data is always shifted out on one clock edge and sampled on the opposite edge of the clock. clock polarity and clock phase relative to data are programmable into the spictl control register and define the transfer format. spiclk has a 22.5 k internal pull-up resistor. spids i input only serial peripheral interface slave device select . an active low signal used to select the processor as an spi slave device. this input signal behaves like a chip select, and is provided by the master device for the slave devices. in multimaster mode the processors spids signal can be driven by a slave device to signal to the processor (as spi master) that an error has occurred, as so me other device is also trying to be the master device. if asserted low when the device is in master mode, it is considered a multimaster error. for a single-master, mu ltiple-slave configuration where flag pins are used, this pin must be tied or pulled high to v ddext on the master device. for processor to processor spi interaction, any of the master processors flag pins can be used to drive the spids signal on the spi slave device. mosi i/o (o/d) (pu) three-state with pull-up enabled spi master out slave in . if the adsp-2136x is configur ed as a master, the mosi pin becomes a data transmit (output) pin, tran smitting output data. if the processor is configured as a slave, the mosi pin becomes a data receive (input) pin, receiving input data. in a spi interconnection, the data is shifted out from the mosi output pin of the master and shifted into the mosi input( s) of the slave(s). mosi has a 22.5 k internal pull-up resistor. miso i/o (o/d) (pu) three-state with pull-up enabled spi master in slave out . if the adsp-2136x is configured as a master, the miso pin becomes a data receive (input) pin, receiving input data. if the processor is configured as a slave, the miso pin becomes a data tr ansmit (output) pin, transmitting output data. in an spi interconnection, the data is shifted out from the miso output pin of the slave and shifted into the miso input pin of the master. miso has a 22.5 k internal pull-up resistor. miso can be configured as o/d by setting the opd bit in the spictl register. note: only one slave is allowed to transmit data at any given time. to enable broadcast transmission to multiple spi-slaves, the processors miso pin may be disabled by setting (=1) bit 5 (dmiso) of the spictl register. bootcfg1C0 i input only boot configuration select . this pin is used to select the boot mode for the processor. the bootcfg pins must be valid before reset is asserted. see table 7 for a description of the boot modes. clkin i input only local clock in . used in conjunction with xtal. clkin is the adsp-2136x clock input. it configures the adsp-2136x to use either its internal clock generator or an external clock source. connecting the necessary components to clkin and xtal enables the internal clock generator. connecting the external clock to clkin while leaving xtal unconnected configures the processors to us e the external clock source such as an external clock oscillator. the core is clocked either by the pll output or this clock input depending on the clkcfg1C0 pin settings. clkin may not be halted, changed, or operated below the specified frequency. xtal o output only 2 crystal oscillator terminal . used in conjunction with clkin to drive an external crystal. clkcfg1C0 i input only core/clkin ratio control . these pins set the start up clock frequency. see table 8 for a description of the clock configuration modes. note that the operating frequency can be changed by programming the pll multiplier and divider in the pmctl register at any time after the core comes out of reset. table 4. pin descriptions (continued) pin type state during and after reset description
rev. a | page 14 of 52 | december 2006 adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 rstout /clkout o output only local clock out/reset out . drives out the core reset signal to an external device. clkout can also be configured as a reset out pin. the functionality can be switched between the pll output clock and reset out by setting bit 12 of the pmctreg register. the default is reset out. reset i/a input only processor reset . resets the adsp-2136x to a known state. upon deassertion, there is a 4096 clkin cycle latency for the pll to lock . after this time, the core begins program execution from the hardware reset vector address. the reset input must be asserted (low) at power-up. tck i input only 3 test clock (jtag) . provides a clock for jtag boundary scan. tck must be asserted (pulsed low) after power-up or held low for proper operation of the processors. tms i/s (pu) three-state with pull-up enabled test mode select (jtag) . used to control the test state machine. tms has a 22.5 k internal pull-up resistor. tdi i/s (pu) three-state with pull-up enabled test data input (jtag) . provides serial data for the boundary scan logic. tdi has a 22.5 k internal pull-up resistor. tdo o three-state 4 test data output (jtag) . serial scan output of the boundary scan path. trst i/a (pu) three-state with pull-up enabled test reset (jtag) . resets the test state machine. trst must be asserted (pulsed low) after power-up or held low for prope r operation of the adsp-2136x. trst has a 22.5 k internal pull-up resistor. emu o (o/d) (pu) three-state with pull-up enabled emulation status . must be connected to the processors jtag emulators target board connector only. emu has a 22.5 k internal pull-up resistor. v ddint p core power supply . nominally +1.2 v dc for the k, b grade models, and 1.0 v dc for the y and w grade models, an d supplies the processors core (13 pins). v ddext p i/o power supply . nominally +3.3 v dc (6 pins). a vdd p analog power supply . nominally +1.2 v dc for the k, b grade models, and 1.0 v dc for the y and w grade models, and supplies the processors internal pll (clock generator). this pin has the same specifications as v ddint , except that added filtering circuitry is required. for more information, see power supplies on page 9. a vss g analog power supply return . gnd g power supply return . (54 pins) 1 rd , wr , and ale are three-stated (and not driven) only when reset is active. 2 output only is a three-state driver wi th its output path always enabled. 3 input only is a three-state driver with both output path and pull-up disabled. 4 three-state is a three-state driver with pull-up disabled. table 4. pin descriptions (continued) pin type state during and after reset description
adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 rev. a | page 15 of 52 | december 2006 address data pins as flags to use these pins as flags (flags15C0) set (=1) bit 20 of the sysctl register to disable th e parallel port. then set (=1) bits 22 to 25 in the sysc tl register accordingly. address/data modes the following table shows the func tionality of the ad pins for 8-bit and 16-bit transfers to the parallel port. for 8-bit data transfers, ale latches address bits a23 C a8 when asserted, fol- lowed by address bits a7 C a0 and data bits d7 C d0 when deasserted. for 16-bit data transf ers, ale latches address bits a15 C a0 when asserted, follo wed by data bits d15 C d0 when deasserted. boot modes core instruction rate to clkin ratio modes for details on processor timing, see timing specifications and figure 6 on page 18 . table 5. ad15C0 to flag pin mapping ad pin flag pin ad pin flag pin ad0 flag8 ad8 flag0 ad1 flag9 ad9 flag1 ad2 flag10 ad10 flag2 ad3 flag11 ad11 flag3 ad4 flag12 ad12 flag4 ad5 flag13 ad13 flag5 ad6 flag14 ad14 flag6 ad7 flag15 ad15 flag7 table 6. address/data mode selection pp data mode ale ad7Cad0 function ad15Cad8 function 8-bit asserted a15Ca8 a23Ca16 8-bit deasserted d7Cd0 a7Ca0 16-bit asserted a7Ca0 a15Ca8 16-bit deasserted d7Cd0 d15Cd8 table 7. boot mode selection bootcfg1C0 booting mode 00 spi slave boot 01 spi master boot 10 parallel port boot via eprom table 8. core instruction rate/clkin ratio selection clkcfg1C0 core to clkin ratio 00 6:1 01 32:1 10 16:1
rev. a | page 16 of 52 | december 2006 adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 adsp-2136x specifications operating conditions electrical characteristics k grade b grade parameter 1 1 specifications subject to change without notice. description min max min max unit v ddint internal (core) supply voltage 1.14 1.26 1.14 1.26 v a vdd analog (pll) supply vo ltage 1.14 1.26 1.14 1.26 v v ddext external (i/o) supply voltage 3.13 3.47 3.13 3.47 v v ih 2 2 applies to input and bid irectional pins: ad15C0, flag3C0, dai_px, spiclk, mosi, miso, spids , bootcfgx, clkcfgx, reset , tck, tms, tdi, trst . high level input voltage @ v ddext = max 2.0 v ddext + 0.5 2.0 v ddext + 0.5 v v il 2 low level input voltage @ v ddext = min C0.5 +0.8 C0.5 +0.8 v v ih _ clkin 3 3 applies to input pin clkin. high level input voltage @ v ddext = max 1.74 v ddext + 0.5 1.74 v ddext + 0.5 v v il _ clkin low level input voltage @ v ddext = min C0.5 +1.19 C0.5 +1.19 v t amb 4, 5 4 see thermal characteristics on page 47 for information on thermal specifications. 5 see engineer-to-engineer note (no. ee-277) for further information. ambient operating temperature 0 +70 C40 +85 c parameter 1 description test conditions min max unit v oh 2 high level output voltage @ v ddext = min, i oh = C1.0 ma 3 2.4 v v ol 2 low level output voltage @ v ddext = min, i ol = 1.0 ma 3 0.4 v i ih 4, 5 high level input current @ v ddext = max, v in = v ddext max 10 a i il 4 low level input current @ v ddext = max, v in = 0 v 10 a i ilpu 5 low level input current pull-up @ v ddext = max, v in = 0 v 200 a i ozh 6, 7 three-state leakage current @ v ddext = max, v in = v ddext max 10 a i ozl 6 three-state leakage current @ v ddext = max, v in = 0 v 10 a i ozlpu 7 three-state leakage current pull-up @ v ddext = max, v in = 0 v 200 a i dd - intyp 8, 9 supply current (internal) t cclk = min, v ddint = nom 800 ma ai dd 10 supply current (analog) a vdd = max 10 ma c in 11, 12 input capacitance f in = 1 mhz, t case = 25c, v in = 1.2 v 4.7 pf 1 specifications subject to change without notice. 2 applies to output and bidir ectional pins: ad15C0, rd , wr , ale, flag3C0, dai_px, spiclk, mosi, miso, emu , tdo, clkout, xtal. 3 see output drive currents on page 46 for typical drive current capabilities. 4 applies to input pins: spids , bootcfgx, clkcfgx, tck, reset , clkin. 5 applies to input pins with 22.5 k internal pull-ups: trst , tms, tdi. 6 applies to three-stateable pins: flag3C0. 7 applies to three-stateable pins with 22.5 k pull-ups: ad15C0, dai_px, spiclk, emu , miso , mosi . 8 typical internal current data reflec ts nominal operating conditions. 9 see engineer-to-engineer note (no. ee-277) for further information. 10 characterized, but not tested. 11 applies to all signal pins. 12 guaranteed, but not tested.
adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 rev. a | page 17 of 52 | december 2006 package information the information presented in figure 5 provides details about the package branding for the adsp-2136x processor. for a complete listing of pr oduct availability, see ordering guide on page 52 . maximum power dissipation see engineer-to-engineer note (ee-277) for detailed thermal and power information regarding maximum power dissipation. for information on package thermal specifications, see thermal characteristics on page 47 . absolute maximum ratings stresses greater than those list ed below may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specifica- tion is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd sensitivity figure 5. typical package brand table 9. package brand information brand key field description t temperature range pp package type z lead free option cc see ordering guide vvvvvv.x assembly lot code n.n silicon revision yyww date code vvvvvv.x n.n tppz-cc s adsp-2136x a yyww country_of_origin parameter rating internal (core) supply voltage (v ddint )C0.3 v to +1.5 v analog (pll) supply voltage (a vdd )C0.3 v to +1.5 v external (i/o) supply voltage (v ddext )C0.3 v to +4.6 v input voltage C0.5 v to +3.8 v output voltage swing C0.5 v to v ddext + 0.5 v load capacitance 200 pf storage temperature range C65 c to +150 c junction temperature under bias 125 c caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the huma n body and test equipment and can di scharge without detection. although the adsp-2136x features proprie tary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance de gradation or loss of functionality.
rev. a | page 18 of 52 | december 2006 adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 timing specifications the adsp-2136xs internal clock (a multiple of clkin) pro- vides the clock signal for timi ng internal memory, processor core, serial ports, and parallel po rt (as required for read/write strobes in asynchrono us access mode). during reset, program the ratio between the processor s internal clock frequency and external (clkin) clock frequency with the clkcfg1C0 pins (see table 8 on page 15 ). to determine switching frequencies for the serial ports, divide down the internal clock, using the programmable divider control of each port (divx for the serial ports). the adsp-2136xs internal clock sw itches at high er frequencies than the system input clock (clk in). to generate the internal clock, the processor uses an internal phase-locked loop (pll). this pll-based clocking minimizes the skew between the sys- tem clock (clkin) signal and the processors internal clock (the clock source for the paralle l port logic and i/o pads). note the definitions of various clock periods that are a function of clkin and the appropriate ratio control shown in table 10 and table 11 . figure 6 shows core to clkin ratios of 6:1, 16:1, and 32:1 with external oscillator or cr ystal. note that more ratios are possible and can be set through software using the power management control register (pmctl). for more information, see the adsp-2136x sharc processo r programming reference . use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the va lues given in this data sheet reflect statistical variations and worst cases. consequently, it is not meaningful to add parameters to derive longer times. see figure 39 on page 46 under test conditions for voltage reference levels. timing requirements apply to signals that are controlled by cir- cuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates correctly with other devices. switching characteristics specify how the processor changes its signals. circuitry external to th e processor must be designed for compatibility with these signal characteristics. switching char- acteristics describe what the processor will do in a given circumstance. use switching charac teristics to en sure that any timing requirement of a device connected to the processor (such as memory) is satisfied. table 10. adsp-2136x clock generation operation timing requirements description calculation clkin input clock 1/t ck cclk core clock 1/t cclk table 11. clock periods timing requirements description 1 t ck clkin clock period t cclk (processor) core clock period t pclk (peripheral) clock period = 2 t cclk t sclk serial port clock period = (t pclk ) sr t spiclk spi clock period = (t pclk ) spir 1 where: sr = serial port-to-peripheral clock ratio (wide range, determined by sport clkdiv) spir = spi-to-peripheral clock ratio (wide range, determined by spibaud register) dai_px = serial port clock spiclk = spi clock figure 6. core clock and system clock relationship to clkin diven 2,4,8,16 pllm delay cclk (core clock) plliclk xtal xtal osc clkout or resetout clk_cfg [1:0] (6:1, 16:1, 32:1) pclk (peripheral clock) indiv 1, 2 2 reset clkin
adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 rev. a | page 19 of 52 | december 2006 power-up sequencing the timing requirements for pr ocessor startup are given in table 12 . table 12. power-up sequencing timing requirements (processor startup) parameter min max unit timing requirements t rstvdd reset low before v ddint /v ddext on 0 ns t ivddevdd v ddint on before v ddext C50 +200 ms t clkvdd 1 clkin valid after v ddint /v ddext valid 0 +200 ms t clkrst clkin valid before reset deasserted 10 2 s t pllrst pll control setup before reset deasserted 20 s switching characteristic t corerst core reset deasserted after reset deasserted 4096t ck + 2 t cclk 3, 4 1 valid v ddint /v ddext assumes that the supplies are fully ramped to their 1.2 volt ra ils and 3.3 volt rails. voltage ramp rates can vary from micros econds to hundreds of milliseconds depending on the desi gn of the power supply subsystem. 2 assumes a stable clkin signal, after meeting worst-case start-up timing of crystal oscillators. refer to your crystal oscillato r manufacturers data sh eet for start-up time. assume a 25 ms maximum oscillator start-up ti me if using the xtal pin and internal osci llator circuit in conjunction with an ex ternal crystal. 3 applies after the power-up sequence is complete. subseque nt resets require a minimum of 4 clkin cycles for reset to be held low in order to properly initialize and propagate default states at all i/o pins. 4 the 4096 cycle count depends on t srst specification in table 14 . if setup time is not met, 1 additional clkin cycle ma y be added to the core reset time, resulting in 4097 cycles maximum. figure 7. power-up sequencing clkin reset t rstvdd rstout v ddext v ddint t pllrst t clkrst t clkvdd t ivddevdd clk_cfg1-0 t corerst
rev. a | page 20 of 52 | december 2006 adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 clock input clock signals the adsp-2136x can use an external clock or a crystal. see the clkin pin description in table 4 on page 12 . the user applica- tion program can configure thea dsp-2136x to use its internal clock generator by connecting th e necessary components to the clkin and xtal pins. figure 9 shows the component connec- tions used for a fundamental fr equency crystal operating in parallel mode. note that the clock rate is achieved using a 16.67 mhz crystal and a pll multiplier ratio 16:1 (cclk:clkin achieves a clock speed of 266.72 mhz). to achieve the full core clock rate, pro- grams need to configure th e multiplier bits in the pmctl register. table 13. clock input parameter 333 mhz unit min max timing requirements t ck clkin period 18 1 1 applies only for clkcfg1C0 = 00 and defaul t values for pll control bits in pmctl. 100 ns t ckl clkin width low 7.5 1 ns t ckh clkin width high 7.5 1 ns t ckrf clkin rise/fall (0.4 v to 2.0 v) 3 ns t cclk 2 2 any changes to pll control bits in the pmctl regis ter must meet core clock timing specification t cclk . cclk period 3.0 1 10 ns t ckj 3,4 3 actual input jitter should be combined with ac specifications for acc urate timing analysis. 4 jitter specification is maximum peak-to -peak time interval error (tie) jitter. clkin jitter tolerance C250 +250 ps figure 8. clock input clkin t ck t ckh t ckl t ckj figure 9. 333 mhz operation (fundamental mode crystal) c1 22pf y1 r1 1m * xtal clkin c2 22pf 24.576mhz r2 47 * r2 should be chosen to limit crystal drive power. refer to crystal manufacturer?s specifications *typical values adsp-2136x
adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 rev. a | page 21 of 52 | december 2006 reset interrupts the following timing specification applies to the flag0, flag1, and flag2 pins when they are config ured as irq0 , irq1 , and irq2 interrupts. table 14. reset parameter min max unit timing requirements t wrst 1 reset pulse width low 4t ck ns t srst reset setup before clkin low 8 ns 1 applies after the power-up sequence is comp lete. at power-up, the proces sors internal phase-locked l oop requires no more than 1 00 s while reset is low, assuming stable v dd and clkin (not including start-up time of external clock oscillator). figure 10. reset clkin reset t wrst t srst table 15. interrupts parameter min max unit timing requirement t ipw irqx pulse width 2 t pclk +2 ns figure 11. interrupts dai20 - 1 flag2 - 0 (irq2 - 0) t ipw
rev. a | page 22 of 52 | december 2006 adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 core timer the following timing specification applies to flag3 when it is configured as the core timer (ctimer). timer pwm_out cycle timing the following timing specification applies to timer0, timer1, and timer2 in pwm_out (pulse-width modulation) mode. timer signals are routed to the dai_p20C1 pins through the sru. therefore, the timing specifications provided below are valid at the dai_p20C1 pins. table 16. core timer parameter min max unit switching characteristic t wctim ctimer pulse width 2 t pclk C 1 ns figure 12. core timer flag3 (ctimer) t wctim table 17. timer pwm_out timing parameter min max unit switching characteristic t pwmo timer pulse width output 2 t pclk C 1 2(2 31 C 1) t pclk ns figure 13. timer pwm_out timing dai_p20 - 1 (timer2 - 0) t pwmo
adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 rev. a | page 23 of 52 | december 2006 timer wdth_cap timing the following timing specification applies to timer0, timer1, and timer2 in wdth_cap (pul se width count and capture) mode. timer signals are routed to the dai_p20C1 pins through the sru. therefore, the timing specification provided below are valid at the dai_p20C1 pins. dai pin to pin direct routing for direct pin connections only (for example, dai_pb01_i to dai_pb02_o). table 18. timer width capture timing parameter min max unit timing requirement t pwi timer pulse width 2 t pclk 2(2 31 C 1) t pclk ns figure 14. timer width capture timing dai_p20-1 (timer2-0) t pwi table 19. dai pin to pin routing parameter min max unit timing requirement t dpio delay dai pin input valid to dai output valid 1.5 10 ns figure 15. dai pin to pin direct routing dai_pn t dpio dai_pm
rev. a | page 24 of 52 | december 2006 adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 precision clock generator (direct pin routing) this timing is only valid when the sru is configured such that the precision clock generator (pcg) takes its inputs directly from the dai pins (via pin buffers) and sends its outputs directly to the dai pins. for the other ca ses, where the pcgs inputs and outputs are not directly routed to/from dai pins (via pin buffers) there is no timing data available. all timing param- eters and switching characteristics apply to external dai pins (dai_p01 C dai_p20). table 20. precision clock generator (direct pin routing) parameter min max unit timing requirement s t pcgip input clock period 20 ns t strig pcg trigger setup before falling edge of pcg input clock 4.5 ns t htrig pcg trigger hold after falling edge of pcg input clock 3ns switching characteristics t dpcgio pcg output clock and frame sync active edge delay after pcg input clock 2.5 10 ns t dtrigclk pcg output clock delay after pcg trigger 2.5 + ((2.5 + d) t pcgip ) 10 + ((2.5 + d) t pcgip )ns t dtrigfs pcg frame sync delay after pcg trigger 2.5 + ((2.5 + d C ph) t pcgip ) 10 + ((2.5 + d C ph) t pcgip )ns t pcgop output clock period 2 t pcgip 1 ns d = fsxdiv, ph = fsxphase. for more information, see the adsp-2136x sharc proces sor hardware reference , precision clock generators chapter. 1 in normal mode, t pcgop (min) = 2 t pcgip . figure 16. precision clock generator (direct pin routing) dai_pn pcg_trigx_i t strig dai_pm pcg_extx_i (clkin) dai_py pcg_clkx_o dai_pz pcg_fsx_o t htrig t dpcgio t dtrigfs t pcgip t pcgop t dtrigclk t dpcgio
adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 rev. a | page 25 of 52 | december 2006 flags the timing specifications provided below apply to the flag3C0 and dai_p20C1 pins, the parallel port, and the serial peripheral interface (spi). see table 4, pin descri ptions, on page 12 for more information on flag use. table 21. flags parameter min max unit timing requirement t fipw flag3C0 in pulse width 2 t pclk + 3 ns switching characteristic t fopw flag3C0 out pulse width 2 t pclk C 1 ns figure 17. flags dai_p20 - 1 (flag3 - 0 in ) (data31 - 0) t fipw dai_p20 - 1 (flag3 - 0 out ) (data31 - 0) t fopw
rev. a | page 26 of 52 | december 2006 adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 memory readparallel port use these specifications for asyn chronous interfacing to memo- ries (and memory-mapped peri pherals) when the adsp-2136x is accessing external memory space. table 22. 8-bit memory read cycle parameter min max unit timing requirements t drs 1 ad7C0 data setup before rd high 3.3 ns t drh ad7C0 data hold after rd high 0 ns t dad 1 ad15C8 address to ad7C0 data valid d + t pclk C 5.0 ns switching characteristics t alew ale pulse width 2 t pclk C 2.0 ns t adas 2 ad15C0 address setup before ale deasserted t pclk C 2.5 ns t rrh delay between rd rising edge to next falling edge h + t pclk C 1.4 ns t alerw ale deasserted to read asserted 2 t pclk C 3.8 ns t rwale read deasserted to ale asserted f + h + 0.5 ns t adah 2 ad15C0 address hold after ale deasserted t pclk C 2.3 ns t alehz 2 ale deasserted to ad7C0 address in high z t pclk t pclk + 3.0 ns t rw rd pulse width d C 2.0 ns t rddrv ad7C0 ale address drive after read high f + h + t pclk C 2.3 ns t adrh ad15C8 address hold after rd high h ns t dawh ad15C8 address to rd high d + t pclk C 4.0 ns d = (data cycle duration = the value set by the ppdur bits (5C1) in the ppctl register) t pclk h = t pclk (if a hold cycle is specified, else h = 0) f = 7 t pclk (if flash_mode is set, else f = 0) t pclk = (peripheral) clock period = 2 t cclk 1 the timing specified here is su fficient to satisfy either t dad or t drs as they are independent. 2 on reset, ale is an active high cycle. however, it can be configured by soft ware to be active low.
adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 rev. a | page 27 of 52 | december 2006 figure 18. read cycle for 8-bit memory timing valid address ad15-8 t adas ad7-0 t alew ale rd t rw wr t adah t adrh t drs t drh t dad t alerw t rwale valid data valid address t rddrv t alehz valid address valid data t rrh t dawh note: memory reads always occur in groups of four between ale cycles. this figure only shows two memory reads in order to provide the necessary timing information. valid address valid address valid address
rev. a | page 28 of 52 | december 2006 adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 table 23. 16-bit memory read cycle parameter min max unit timing requirements t drs ad15C0 data setup before rd high 3.3 ns t drh ad15C0 data hold after rd high 0 ns switching characteristics t alew ale pulse width 2 t pclk C 2.0 ns t adas 1 ad15C0 address setup before ale deasserted t pclk C 2.5 ns t alerw ale deasserted to read asserted 2 t pclk C 3.8 ns t rrh 2 delay between rd rising edge to next falling edge h + t pclk C 1.4 ns t rwale read deasserted to ale asserted f + h + 0.5 ns t rddrv ale address drive after read high f + h + t pclk C 2.3 ns t adah 1 ad15C0 address hold after ale deasserted t pclk C 2.3 ns t alehz 1 ale deasserted to address/data15C0 in high z t pclk t pclk + 3.0 ns t rw rd pulse width d C 2.0 ns d = (data cycle duration = the value set by the ppdur bits (5C1) in the ppctl register) t pclk h = t pclk (if a hold cycle is specified, else h = 0) f = 7 t pclk (if flash_mode is set, else f = 0) t pclk = (peripheral) clock period = 2 t cclk 1 on reset, ale is an active high cycle. however, it can be configured by soft ware to be active low. 2 this parameter is only avai lable when in empp = 0 mode. figure 19. read cycle for 16-bit memory timing ad15 - 0 wr t drs t drh t alehz t adah t adas valid address valid data valid data t alew t rw t alerw t rrh ale rd t rwale t rddrv valid address note: for 16-bit memory reads, when empp 0, only one rd pulse occurs between ale cycles. when empp = 0, multiple rd pulses occur between ale cycles. for complete information, see the adsp-2136x sharc processor hardware reference.
adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 rev. a | page 29 of 52 | december 2006 memory writeparallel port use these specifications for asyn chronous interfacing to memo- ries (and memory-mapped peripherals) when the adsp-2136x is accessing external memory space. table 24. 8-bit memory write cycle parameter min max unit switching characteristics t alew ale pulse width 2 t pclk C 2.0 ns t adas 1 ad15C0 address setup before ale deasserted t pclk C 2.8 ns t alerw ale deasserted to write asserted 2 t pclk C 3.8 ns t rwale write deasserted to ale asserted h + 0.5 ns t wrh delay between wr rising edge to next wr falling edge f + h + t pclk C 2.3 ns t adah 1 ad15C0 address hold after ale deasserted t pclk C 0.5 ns t ww wr pulse width d C f C 2.0 ns t adwl ad15C8 address to wr low t pclk C 2.8 ns t adwh ad15C8 address hold after wr high h ns t dws ad7C0 data setup before wr high d C f + t pclk C 4.0 ns t dwh ad7C0 data hold after wr high h ns t dawh ad15C8 address to wr high d C f + t pclk C 4.0 ns d = (data cycle duration = the value set by the ppdur bits (5C1) in the ppctl register) t pclk . h = t pclk (if a hold cycle is specified, else h = 0) f = 7 t pclk (if flash_mode is set, else f = 0) . if flash_mode is set, d must be 9 t pclk . t pclk = (peripheral) clock period = 2 t cclk 1 on reset, ale is an active high cycle. however, it can be configured by soft ware to be active low. figure 20. write cycle for 8-bit memory timing ad15 - 8 valid address valid address t adas ad7 - 0 ale rd wr t adah t adwh t adwl valid data t dawh t wrh t rwale valid address valid data t alew t alerw t ww t dws t dwh valid address note: memory writes always occur in groups of four between ale cycles. this figure only shows two memory writes in order to provide the necessary timing information.
rev. a | page 30 of 52 | december 2006 adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 table 25. 16-bit memory write cycle parameter min max unit switching characteristics t alew ale pulse width 2 t pclk C 2.0 ns t adas 1 ad15C0 address setup before ale deasserted t pclk C 2.5 ns t alerw ale deasserted to write asserted 2 t pclk C 3.8 ns t rwale write deasserted to ale asserted h + 0.5 ns t wrh 2 delay between wr rising edge to next wr falling edge f + h + t pclk C 2.3 ns t adah 1 ad15C0 address hold after ale deasserted t pclk C 2.3 ns t ww wr pulse width d C f C 2.0 ns t dws ad15C0 data setup before wr high d C f + t pclk C 4.0 ns t dwh ad15C0 data hold after wr high h ns d = (data cycle duration = the value set by the ppdur bits (5C1) in the ppctl register) t pclk . h = t pclk (if a hold cycle is specified, else h = 0) f = 7 t pclk (if flash_mode is set, else f = 0) . if flash_mode is set, d must be 9 t pclk . t pclk = (peripheral) clock period = 2 t cclk 1 on reset, ale is an active high cycle. however, it can be configured by soft ware to be active low. 2 this parameter is only avai lable when in empp = 0 mode. figure 21. write cycle for 16-bit memory timing ad15 - 0 valid address valid data t adas ale rd wr t adah t wrh t rwale t alew t alerw t ww t dws t dwh valid data valid address note: for 16-bit memory writes, when empp 0, only one wr pulse occurs between ale cycles. when empp = 0, multiple wr pulses occur between ale cycles. for complete information, see the adsp-2136x sharc processor hardware reference.
adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 rev. a | page 31 of 52 | december 2006 serial ports to determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) sclk width. serial port signals (sclk, fs, data channel a, data channel b) are routed to the dai_p20C1 pins using the sru. therefore, the timing specifications provided below are valid at the dai_p20C1 pins. table 26. serial portsexternal clock parameter min max unit timing requirements t sfse 1 fs setup before sclk (externally generated fs in either transmit or receive mode) 2.5 ns t hfse 1 fs hold after sclk (externally generated fs in either transmit or receive mode) 2.5 ns t sdre 1 receive data setup before receive sclk 2.5 ns t hdre 1 receive data hold after sclk 2.5 ns t sclkw sclk width 12 ns t sclk sclk period 24 ns switching characteristics t dfse 2 fs delay after sclk (internally generated fs in either transmit or receive mode) 9.5 ns t hofse 2 fs hold after sclk (internally generated fs in either transmit or receive mode) 2 ns t ddte 2 transmit data delay after transmit sclk 9.5 ns t hdte 2 transmit data hold af ter transmit sclk 2 ns 1 referenced to sample edge. 2 referenced to drive edge. table 27. serial portsinternal clock parameter min max unit timing requirements t sfsi 1 fs setup before sclk (externally generated fs in either transmit or receive mode) 7 ns t hfsi 1 fs hold after sclk (externally generated fs in either transmit or receive mode) 2.5 ns t sdri 1 receive data setup before sclk 7 ns t hdri 1 receive data hold after sclk 2.5 ns switching characteristics t dfsi 2 fs delay after sclk (internally generated fs in transmit mode) 3 ns t hofsi 2 fs hold after sclk (internally generated fs in transmit mode) C1.0 ns t dfsir 2 fs delay after sclk (internally generated fs in receive mode) 8 ns t hofsir 2 fs hold after sclk (internally generated fs in receive mode) C1.0 ns t ddti 2 transmit data delay after sclk 3 ns t hdti 2 transmit data hold after sclk C1.0 ns t sclkiw transmit or receive sclk width 0.5t sclk C 2 0.5t sclk + 2 ns 1 referenced to the sample edge. 2 referenced to drive edge.
rev. a | page 32 of 52 | december 2006 adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 table 28. serial portsenable and three-state parameter min max unit switching characteristics t ddten 1 data enable from external transmit sclk 2 ns t ddtte 1 data disable from external transmit sclk 7 ns t ddtin 1 data enable from internal transmit sclk C1 ns 1 referenced to drive edge. table 29. serial portsexternal late frame sync parameter min max unit switching characteristics t ddtlfse 1 data delay from late external transmit fs or external receive fs with mce = 1, mfd = 0 9 ns t ddtenfs 1 data enable for mce = 1, mfd = 0 0.5 ns 1 the t ddtlfse and t ddtenfs parameters apply to left-justifi ed sample pair as well as dsp serial mode, and mce = 1, mfd = 0. figure 22. external late frame sync 1 1 this figure reflects changes made to su pport left-justified sample pair mode. drive sample drive dai_p20 - 1 (sclk) dai_p20 - 1 (fs) dai_p20 - 1 (data channel a/b) drive sample drive late external transmit fs external receive fs with mce = 1, mfd = 0 1st bit 2nd bit dai_p20 - 1 (sclk) dai_p20 - 1 (fs) 1st bit 2nd bit t hfse/i t sfse/i t ddte/i t ddtenfs t ddtlfse t hdte/i t sfse/i t ddte/i t ddtenfs t ddtlfse t hdte/i dai_p20 - 1 (data channel a/b) note: serial port signals (sclk, fs, data channel a/b ) are routed to the dai_p20-1 pins using the sru. the timing specifications provided here are valid at the dai_p20-1 pins. t hfse/i
adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 rev. a | page 33 of 52 | december 2006 figure 23. serial ports drive edge dai_p20 - 1 sclk (int) drive edge drive edge sclk dai_p20 - 1 sclk (ext) t ddtte t ddten t ddtin dai_p20 - 1 (data channel a/b) dai_p20 - 1 (data channel a/b) dai_p20 - 1 (sclk) dai_p20 - 1 (fs) drive edge sample edge data receive?internal clock data receive ? e x ternal clock drive edge sample edge note: either the rising edge or falling edge of sclk (external), sclk (internal) can be used as the active sampling edge. t sdri t hdri t sfsi t hfsi t dfsir t hofsr t sclkiw t sdre t hdre t sfse t hfse t dfse t sclkw t hofse dai_p20 - 1 (data channel a/b) t ddti drive edge sample edge data transmit?internal clock t sfsi t hfsi t dfsi t hofsi t sclkiw t hdti note: either the rising edge or falling edge of sclk (external), sclk (internal) can be used as the active sampling edge. t ddte drive edge sample edge data transmit?external clock t sfse t hfse t dfse t hofse t sclkw t hdte dai_p20 - 1 (sclk) dai_p20 - 1 (fs) dai_p20 - 1 (data channel a/b) dai_p20 - 1 (sclk) dai_p20 - 1 (fs) dai_p20 - 1 (data channel a/b) dai_p20 - 1 (sclk) dai_p20 - 1 (fs) dai_p20 - 1 (data channel a/b)
rev. a | page 34 of 52 | december 2006 adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 input data port (idp) the timing requirements for the idp are given in table 30 . idp signals (sclk, fs, sdata) are routed to the dai_p20C1 pins using the sru. therefore, the ti ming specifications provided below are valid at the dai_p20C1 pins. table 30. idp parameter min max unit timing requirements t sisfs 1 fs setup before sclk rising edge 3 ns t sihfs 1 fs hold after sclk rising edge 3 ns t sisd 1 sdata setup before sclk rising edge 3 ns t sihd 1 sdata hold after sclk rising edge 3 ns t idpclkw clock width 9 ns t idpclk clock period 24 ns 1 data, sclk, fs can come from any of the da i pins. sclk and fs can also come via pcg or sports. pcgs input can be either clkin or any of the dai pins. figure 24. idp master timing dai_p20 - 1 (sclk) dai_p20 - 1 (fs) sample edge t sisfs t sihfs t idpclk dai_p20 - 1 (sdata) t idpclkw t sisd t sihd
adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 rev. a | page 35 of 52 | december 2006 parallel data acquisition port (pdap) the timing requirements for the pdap are provided in table 31 . pdap is the parallel mode operation of channel 0 of the idp. for details on the oper ation of the idp, see the idp chapter of the adsp-2136x sharc processor hardware reference . note that the most significant 16 bits of external pdap data can be provid ed through either the parallel port ad15C0 or the dai_p20C5 pi ns. the remaining 4 bits can only be sourced through dai_p4 C1. the timing below is valid at the dai_p20C1 pins or at the ad15C0 pins. table 31. parallel data acquisition port (pdap) parameter min max unit timing requirements t spclken 1 pdap_clken setup before pdap_clk sample edge 2.5 ns t hpclken 1 pdap_clken hold after pdap_clk sample edge 2.5 ns t pdsd 1 pdap_dat setup before sclk pdap_clk sample edge 3.0 ns t pdhd 1 pdap_dat hold after sclk pdap_clk sample edge 2.5 ns t pdclkw clock width 7.0 ns t pdclk clock period 24 ns switching characteristics t pdhldd delay of pdap strobe after last pdap_clk capture edge for a word 2 t pclk C 1 ns t pdstrb pdap strobe pulse width 2 t pclk C 1.5 ns 1 source pins of data are addr7C0, data7C0, or dai pins. source pins for sclk and fs are: 1) dai pins, 2) clkin through pcg, or 3) dai pins through pcg. figure 25. pdap timing dai_p20 - 1 (pdap_clk) sample edge t pdsd t pdhd t spclken t hpclken t pdclkw data dai_p20 - 1 (pdap_clken) t pdstrb t pdhldd dai_p20 - 1 (pdap_strobe) t pdclk
rev. a | page 36 of 52 | december 2006 adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 pulse-width modulation generators sample rate converterserial input port the src input signals (sclk, fs , and sdata) are routed from the dai_p20C1 pins using the sru. therefore, the timing spec- ifications provided in table 33 are valid at the dai_p20C1 pins. this feature is not availa ble on the ADSP-21363 models. table 32. pwm timing parameter min max unit switching characteristics t pwmw pwm output pulse width t pclk C 2 (2 16 C 2) t pclk C 2 ns t pwmp pwm output period 2 t pclk C 1.5 (2 16 C 1) t pclk ns figure 26. pwm timing pwm outputs t pwmw t pwmp table 33. src, serial input port parameter min max unit timing requirements t srcsfs 1 fs setup before sclk rising edge 3 ns t srchfs 1 fs hold after sclk rising edge 3 ns t srcsd 1 sdata setup before sclk rising edge 3 ns t srchd 1 sdata hold after sclk rising edge 3 ns t srcclkw clock width 36 ns t srcclk clock period 80 ns 1 data, sclk, fs can come from any of the da i pins. sclk and fs can also come via pcg or sports. pcgs input can be either clkin or any of the dai pins. figure 27. src serial input port timing dai_p20 - 1 (sclk) dai_p20 - 1 (fs) sample edge t srcsfs t srchfs t srcclk dai_p20 - 1 (sdata) t srcclkw t srcsd t srchd
adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 rev. a | page 37 of 52 | december 2006 sample rate converterserial output port for the serial output port, the fr ame-sync is an input and should meet setup and hold times with regard to sclk on the output port. the serial data output, sdata, has a hold time and delay specification with regard to sclk. note that sclk rising edge is the sampling edge and the falling edge is the drive edge. table 34. src, serial output port parameter min max unit timing requirements t srcsfs 1 fs setup before sclk rising edge 3 ns t srchfs 1 fs hold after sclk rising edge 3 ns switching characteristics t srctdd 1 transmit data delay after sclk falling edge 10.5 ns t srctdh 1 transmit data hold after sclk falling edge 2 ns 1 data, sclk, fs can come from any of the da i pins. sclk and fs can also come via pcg or sports. pcgs input can be either clkin or any of the dai pins. figure 28. src serial output port timing dai_p20 - 1 (sclk) dai_p20 - 1 (fs) t srcsfs t srchfs dai_p20 - 1 (sdata) t srctdd t srctdh sample edge t srcclk t srcclkw
rev. a | page 38 of 52 | december 2006 adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 spdif transmitter serial data input to the spdif transmitter can be formatted as left-justified, i 2 s, or right-justified with word widths of 16, 18, 20, or 24 bits. the following se ctions provide timing for the transmitter. this feature is not available on the ADSP-21363 models. spdif transmitterserial input waveforms figure 29 shows the right-justified mode. lrclk is hi for the left channel and lo for the right channel. data is valid on the rising edge of sclk. the msb is delayed 12-bit clock periods (in 20-bit output mode) or 16-bit clock periods (in 16-bit output mode) from an lrclk transition, so that when there are 64 sclk periods per lrclk period , the lsb of the data will be right-justified to the next lrclk transition. figure 30 shows the default i 2 s-justified mode. lrclk is lo for the left channel and hi for the right channel. data is valid on the rising edge of sclk. the msb is left-justified to an lrclk transition but with a single sclk period delay. figure 31 shows the left-justified mode . lrclk is hi for the left channel and lo for the right channel. data is valid on the rising edge of sclk. the msb is left-jus tified to an lrclk transition with no msb delay. figure 29. right -justified mode lrclk sclk sdata left channel right channel msb-1 msb-2 lsb+2 lsb+1 lsb msb msb-1 msb-2 lsb+2 lsb+1 lsb lsb msb figure 30. i 2 s-justified mode msb-1 msb-2 lsb+2 lsb+1 lsb lrclk sclk sdata left channel right channel msb msb-1 msb-2 lsb+2 lsb+1 lsb msb msb figure 31. left-justified mode lrclk sclk sdata left channel right channel ms b-1 ms b-2 lsb+2 lsb+1 lsb msb msb-1 msb-2 lsb+2 lsb+1 lsb msb msb+1 msb
adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 rev. a | page 39 of 52 | december 2006 spdif transmitter input data timing the timing requirements for the input port are given in table 35 . input signals (sclk, fs, and sdata) are routed to the dai_p20C1 pins using the sru. therefore, the timing spec- ifications provided below are valid at the dai_p20C1 pins. oversampling clock (txclk) switching characteristics spdif transmitter has an over sampling clock. this txclk input is divided down to generate the biphase clock. table 35. spdif transmitter input data timing parameter min max unit timing requirements t sisfs 1 fs setup before sclk rising edge 3 ns t sihfs 1 fs hold after sclk rising edge 3 ns t sisd 1 sdata setup before sclk rising edge 3 ns t sihd 1 sdata hold after sclk rising edge 3 ns t sisclkw clock width 36 ns t sisclk clock period 80 ns t sitxclkw transmit clock width 9 ns t sitxclk transmit clock period 20 ns 1 data, sclk, fs can come from any of the da i pins. sclk and fs can also come via pcg or sports. pcgs input can be either clkin or any of the dai pins. figure 32. spdif transmitter input timing dai_p20 - 1 (sclk) dai_p20 - 1 (fs) sample edge t sisd t sisfs t sisclkw dai_p20 - 1 (sdata) dai_p20 - 1 (txclk) t sihd t sihfs t sitxclkw t sitxclk table 36. oversampling clock (txclk) switching characteristics parameter min max unit txclk frequency for txclk = 768 fs 147.5 mhz txclk frequency for txclk = 512 fs 98.4 mhz txclk frequency for txclk = 384 fs 73.8 mhz txclk frequency for txclk = 256 fs 49.2 mhz frame rate 192.0 khz
rev. a | page 40 of 52 | december 2006 adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 spdif receiver the following section describes timing as it relates to the spdif receiver. this feature is not available on the ADSP-21363 models. internal digital pll mode in the internal digital phase-lock ed loop mode the internal pll (digital pll) generates the 512 fs clock. table 37. spdif receiver output ti ming (internal digital pll mode) parameter min max unit switching characteristics t dfsi lrclk delay after sclk 5 ns t hofsi lrclk hold after sclk C2 ns t ddti transmit data delay after sclk 5 ns t hdti transmit data hold after sclk C2 ns t sclkiw 1 transmit sclk width 38 ns t cclk core clock period 5 ns 1 sclk frequency is 64 fs where fs = the frequency of lrclk. figure 33. spdif receiver internal digital pll mode timing drive edge sample edge dai_p20 - 1 (sclk) dai_p20 - 1 (fs) dai_p20 - 1 (data channel a/b) t sclkiw t dfsi t ddti t hofsi t hdti
adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 rev. a | page 41 of 52 | december 2006 spi interfacemaster the adsp-2136x contains two spi ports. the primary has dedi- cated pins and the secondary is available through the dai. the timing provided in table 38 and table 39 applies to both. table 38. spi interface protocolmaster switching and timing specifications parameter min max unit timing requirements t sspidm data input valid to spiclk edge (data input setup time) 5.2 ns t sspidm data input valid to spiclk edge (data input setup time) (spi2) 8.2 ns t hspidm spiclk last sampling edge to data input not valid 2ns switching characteristics t spiclkm serial clock cycle 8 t pclk C 2 ns t spichm serial clock high period 4 t pclk C 2 ns t spiclm serial clock low period 4 t pclk C 2 ns t ddspidm spiclk edge to data out valid (data out delay time) 3.0 ns t ddspidm spiclk edge to data out valid (data out delay time) (spi2) 8.0 ns t hdspidm spiclk edge to data out not valid (data out hold time) 2ns t sdscim flag3C0in (spi device select) low to first spiclk edge 4 t pclk C 2.5 ns t sdscim flag3C0in (spi device select) low to first spiclk edge (spi2) 4 t pclk C 2.5 ns t hdsm last spiclk edge to flag3C0in high 4 t pclk C 2 ns t spitdm sequential transfer delay 4 t pclk C 1 ns
rev. a | page 42 of 52 | december 2006 adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 figure 34. spi master timing lsb valid msb valid t sspidm t hspidm t hdspidm lsb msb t hspidm t ddspidm mosi (output) miso (input) flag3-0 (output) spiclk (cp = 0) (output) spiclk (cp = 1) (output) t spichm t spiclm t spiclm t spiclkm t spichm t hdsm t spitdm t hdspidm lsb valid lsb msb msb valid t hspidm t ddspidm mosi (output) miso (input) t sspidm cphase = 1 cphase = 0 t sdscim t sspidm
adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 rev. a | page 43 of 52 | december 2006 spi interfaceslave table 39. spi interface protocolslave switching and timing specifications parameter min max unit timing requirements t spiclks serial clock cycle 4 t pclk C 2 ns t spichs serial clock high period 2 t pclk C 2 ns t spicls serial clock low period 2 t pclk C 2 ns t sdsco spids assertion to first spiclk edge cphase = 0 cphase = 1 2 t pclk 2 t pclk ns ns t hds last spiclk edge to spids not asserted, cphase = 0 2 t pclk ns t sspids data input valid to spiclk edge (data input setup time) 2 ns t hspids spiclk last sampling edge to data input not valid 2 ns t sdppw spids deassertion pulse width (cphase = 0) 2 t pclk ns switching characteristics t dsoe spids assertion to data out active 0 5 ns t dsoe 1 spids assertion to data out active (spi2) 0 8 ns t dsdhi spids deassertion to data high impedance 0 5 ns t dsdhi 1 spids deassertion to data high impedance (spi2) 0 8.6 ns t ddspids spiclk edge to data out valid (data out delay time) 9.5 ns t hdspids spiclk edge to data out not valid (data out hold time) 2 t pclk ns t dsov spids assertion to data out valid (cphase = 0) 5 t pclk ns 1 the timing for these parameters applies wh en the spi is routed through the signal routing unit. for more information, see the adsp-2136x sharc processor hardware reference , serial peripheral interface port chapter.
rev. a | page 44 of 52 | december 2006 adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 figure 35. spi slave timing t hspids t ddspids t dsdhi lsb msb msb valid t dsoe t ddspids t hdspids miso (output) mosi (input) t sspids spids (input) spiclk (cp = 0) (input) spiclk (cp = 1) (input) t sdsco t spichs t spicls t spicls t spiclks t hds t spichs t sspids t hspids t dsdhi lsb valid msb msb valid t dsoe t ddspids miso (output) mosi (input) t sspids lsb valid lsb cphase = 1 cphase = 0 t sdppw t dsov t hdspids
adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 rev. a | page 45 of 52 | december 2006 jtag test access port and emulation table 40. jtag test access port and emulation parameter min max unit timing requirements t tck tck period t ck ns t stap tdi, tms setup before tck high 5 ns t htap tdi, tms hold after tck high 6 ns t ssys 1 system inputs setup before tck high 7 ns t hsys 1 system inputs hold after tck high 18 ns t trstw trst pulse width 4t ck ns switching characteristics t dtdo tdo delay from tck low 7 ns t dsys 2 system outputs delay after tck low t ck 2 + 7 ns 1 system inputs = ad15C0, spids , clkcfg1C0, reset , bootcfg1C0, miso, mosi, spiclk, dai_px, flag3C0. 2 system outputs = miso, mosi, spiclk, dai_px, ad15C0, rd , wr , flag3C0, clkout, emu , ale. figure 36. ieee 1149.1 jtag test access port system outputs tck tms tdi tdo system inputs t stap t tck t htap t dtdo t ssys t hsys t dsys
adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 rev. a | page 46 of 52 | december 2006 output drive currents figure 37 shows typical i-v characteri stics for the output driv- ers of the adsp-2136x. the curves represent the current drive capability of the output drivers as a function of output voltage. test conditions the ac signal specifications (timing parameters) appear in table 14 on page 21 through table 40 on page 45 . these include output disable time, output enable time, and capacitive loading. the timing specifications for the sharc apply for the voltage reference levels in figure 38 . timing is measured on signals wh en they cross the 1.5 v level as described in figure 39 . all delays (in nanoseconds) are mea- sured between the point that the first signal reaches 1.5 v and the point that the second signal reaches 1.5 v. capacitive loading output delays and holds are based on standard capacitive loads: 30 pf on all pins (see figure 38 ). figure 42 shows graphically how output delays and holds vary with load capacitance. the graphs of figure 40 , figure 41 , and figure 42 may not be linear outside the ranges shown for typical output delay vs. load capacitance and typical output rise time (20% to 80%, v = min) vs. load capacitance. figure 37. adsp-2136x typical drive figure 38. equivalent device loading for ac measurements (includes all fixtures) figure 39. voltage reference levels for ac measurements sweep (v ddext ) voltage (v) - 20 03.5 0.5 1.5 2.5 0 - 40 - 30 20 40 - 10 s o u r c e ( v d d e x t ) c u r r e n t ( m a ) v ol 3.11v, +125c 3.3v, +25c 3.47v, - 45c v oh 30 10 3.11v, +125c 3.3v, +25c 3.47v, - 45c 1.0 2.0 3.0 1.5v 30pf to output pin 50 input or output 1.5v 1.5v figure 40. typical output rise/fall time (20% to 80%, v ddext = max) figure 41. typical output rise/fall time (20% to 80%, v ddext = min) load capacitance (pf) 8 0 0 100 250 12 4 2 10 6 r i s e a n d f a l l t i m e s ( n s ) 200 150 50 fall y = 0.0467x + 1.6323 y = 0.045x + 1.524 rise load capacitance (pf) 12 0 50 100 150 200 250 10 8 6 4 r i s e a n d f a l l t i m e s ( n s ) 2 0 rise fall y = 0.049x + 1.5105 y = 0.0482x + 1.4604
adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 rev. a | page 47 of 52 | december 2006 thermal characteristics the adsp-2136x processor is ra ted for performance over the temperature range specified in operating conditions on page 16 . table 41 and table 42 airflow measurements comply with jedec standards jesd51-2 and jesd51-6 and the junction-to- board measurement complies with jesd51-8. test board and thermal via design comply wi th jedec standards jesd51-9 (bga). the junction-to-case me asurement complies with mil- std-883. all measurements use a 2s2p jedec test board. industrial applications using the bga package require thermal vias, to an embedded ground plane, in the pcb. refer to jedec standard jesd51-9 for printed ci rcuit board thermal ball land and thermal via design information. to determine the junction temperature of the device while on the application pcb, use: where: t j = junction temperature ( c) t t = case temperature ( c) measured at the top center of the package jt = junction-to-top (of package) characterization parameter is the typical value from table 41 . p d = power dissipation (see ee note no. ee-277 for more information). values of ja are provided for package comparison and pcb design considerations. values of jc are provided for package comparison and pcb design considerations when an external heat sink is required. note that the thermal characteristics values provided in table 41 and table 42 are modeled values. figure 42. typical output delay or hold vs. load capacitance (at ambient temperature) load capacitance (pf) 0 200 50 100 150 10 8 o u t p u t d e l a y o r h o l d ( n s ) 6 0 4 2 - 2 y = 0.0488x - 1.5923 - 4 t j t t jt p d () + = table 41. thermal characteristics for bga (no thermal vias in pcb) parameter condition typical unit ja airflow = 0 m/s 25.40 c/w jma airflow = 1 m/s 21.90 c/w jma airflow = 2 m/s 20.90 c/w jc 5.07 c/w jt airflow = 0 m/s 0.140 c/w jmt airflow = 1 m/s 0.330 c/w jmt airflow = 2 m/s 0.410 c/w table 42. thermal characteristics for bga (thermal vias in pcb) parameter condition typical unit ja airflow = 0 m/s 23.40 c/w jma airflow = 1 m/s 20.00 c/w jma airflow = 2 m/s 19.20 c/w jc 5.00 c/w jt airflow = 0 m/s 0.130 c/w jmt airflow = 1 m/s 0.300 c/w jmt airflow = 2 m/s 0.360 c/w
rev. a | page 48 of 52 | december 2006 adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 136-ball bga pin configurations the following table shows th e adsp-2136xs pin names and their default function after reset (in parentheses). table 43. bga pin assignments ball name ball no. ball name ball no. ball name ball no. ball name ball no. clkcfg0 a01 clkcfg1 b01 bootcfg1 c01 v ddint d01 xtal a02 gnd b02 bootcfg0 c02 gnd d02 tms a03 v ddext b03 gnd c03 gnd d04 tck a04 clkin b04 gnd c12 gnd d05 tdi a05 trst b05 gnd c13 gnd d06 clkout a06 a vss b06 v ddint c14 gnd d09 tdo a07 a vdd b07 gnd d10 emu a08 v ddext b08 gnd d11 mosi a09 spiclk b09 gnd d13 miso a10 reset b10 v ddint d14 spids a11 v ddint b11 v ddint a12 gnd b12 gnd a13 gnd b13 gnd a14 gnd b14 v ddint e01 flag1 f01 ad7 g01 ad6 h01 gnd e02 flag0 f02 v ddint g02 v ddext h02 gnd e04 gnd f04 v ddext g13 dai_p18 (sd5b) h13 gnd e05 gnd f05 dai_p19 (sclk45) g14 dai_p17 (sd5a) h14 gnd e06 gnd f06 gnd e09 gnd f09 gnd e10 gnd f10 gnd e11 gnd f11 gnd e13 flag2 f13 flag3 e14 dai_p20 (sfs45) f14
adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 rev. a | page 49 of 52 | december 2006 ad5 j01 ad3 k01 ad2 l01 ad0 m01 ad4 j02 v ddint k02 ad1 l02 wr m02 gnd j04 gnd k04 gnd l04 gnd m03 gnd j05 gnd k05 gnd l05 gnd m12 gnd j06 gnd k06 gnd l06 dai_p12 (sd3b) m13 gnd j09 gnd k09 gnd l09 dai_p13 (sclk23) m14 gnd j10 gnd k10 gnd l10 gnd j11 gnd k11 gnd l11 v ddint j13 gnd k13 gnd l13 dai_p16 (sd4b) j14 dai_p15 (sd4a) k14 dai_p14 (sfs23) l14 ad15 n01 ad14 p01 ale n02 ad13 p02 rd n03 ad12 p03 v ddint n04 ad11 p04 v ddext n05 ad10 p05 ad8 n06 ad9 p06 v ddint n07 dai_p1 (sd0a) p07 dai_p2 (sd0b) n08 dai_p3 (sclk0) p08 v ddext n09 dai_p5 (sd1a) p09 dai_p4 (sfs0) n10 dai_p6 (sd1b) p10 v ddint n11 dai_p7 (sclk1) p11 v ddint n12 dai_p8 (sfs1) p12 gnd n13 dai_p9 (sd2a) p13 dai_p10 (sd2b) n14 dai_p11 (sd3a) p14 table 43. bga pin assignments (continued) ball name ball no. ball name ball no. ball name ball no. ball name ball no.
adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 rev. a | page 50 of 52 | december 2006 figure 43. bga pin assignments (bottom view, summary) figure 44. bga pin assignments (top view, summary) a vss v ddint v ddext i/o signals a vdd gnd * * use the center block of ground pins to provide thermal pathways to your printed circuit board?s ground plane. key 1 2 3 4 5 6 7 8 9 10 11 12 14 13 p n m l k j h g f e d c b a a vss v ddint v ddext i/o signals a vdd gnd * * use the center block of ground pins to provide thermal pathways to your printed circuit board?s ground plane. key 123456789101112 14 13 p n m l k j h g f e d c b a
adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 rev. a | page 51 of 52 | december 2006 outline dimensions the adsp-2136x is available in a 136-ball bga package. surface mount design table 44 is provided as an aide to pcb design. for industry- standard design recommendations, refer to ipc-7351, generic requirements for surface mount design and land pattern standard . figure 45. 136-ball chip scale package ball grid array [csp_bga](bc-136-2) seating plane 0.25 min detail a 0.50 0.45 0.40 (ball diameter) detail a 1.70 max 1. dimensions are in milimeters (mm). 2. the actual position of the ball grid is within 0.15 mm of its ideal position relative to the package edges. 3. compliant to jedec standard mo-205-ae, except for the ball diameter. 4. center dimensions are nominal. a b c d e f g h j k l m n p 10987654321 13 14 11 12 0.80 bsc typ 10.40 bsc sq pin a1 indicator bottom view top view 12.00 bsc sq 0.12 max (ball coplanarity) 0.80 bsc typ 0.80 bsc typ table 44. bga data for use with surface mount design package ball attach type solder mask opening ball pad size 136-ball grid array (bc-136-2) solder mask defined 0.40 mm diameter 0.53 mm diameter
rev. a | page 52 of 52 | december 2006 ? 2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06359-0-12/06(a) adsp-21362/ADSP-21363/adsp-21364/adsp-21365/adsp-21366 ordering guide model temperature range 1 1 referenced temperature is ambient temperature. instruction rate on-chip sram rom operating voltage internal/external package description package option adsp-21362kbc-1aa 0 c to +70 c 333 mhz 3m bit 4m bit 1.2 v/3.3 v 136-ball csp-bga bc-136-2 adsp-21362kbcz-1aa 2 2 z = pb-free part. 0 c to +70 c 333 mhz 3m bit 4m bit 1.2 v/3.3 v 136-ball csp-bga bc-136-2 adsp-21362bbc-1aa C40 c to +85 c 333 mhz 3m bit 4m bit 1.2 v/3.3 v 136-ball csp-bga bc-136-2 adsp-21362bbcz-1aa 2 C40 c to +85 c 333 mhz 3m bit 4m bit 1.2 v/3.3 v 136-ball csp-bga bc-136-2 adsp-21362wbbcz-1a 2 C40 c to +85 c 333 mhz 3m bit 4m bit 1.2 v/3.3 v 136-ball csp-bga bc-136-2 ADSP-21363kbc-1aa 0 c to +70 c 333 mhz 3m bit 4m bit 1.2 v/3.3 v 136-ball csp-bga bc-136-2 ADSP-21363kbcz-1aa 2 0 c to +70 c 333 mhz 3m bit 4m bit 1.2 v/3.3 v 136-ball csp-bga bc-136-2 ADSP-21363bbc-1aa C40 c to +85 c 333 mhz 3m bit 4m bit 1.2 v/3.3 v 136-ball csp-bga bc-136-2 ADSP-21363bbcz-1aa 2 C40 c to +85 c 333 mhz 3m bit 4m bit 1.2 v/3.3 v 136-ball csp-bga bc-136-2 ADSP-21363wbbcz-1a 2 C40 c to +85 c 333 mhz 3m bit 4m bit 1.2 v/3.3 v 136-ball csp-bga bc-136-2 adsp-21364kbc-1aa 0 c to +70 c 333 mhz 3m bit 4m bit 1.2 v/3.3 v 136-ball csp-bga bc-136-2 adsp-21364kbcz-1aa 2 0 c to +70 c 333 mhz 3m bit 4m bit 1.2 v/3.3 v 136-ball csp-bga bc-136-2 adsp-21364bbc-1aa C40 c to +85 c 333 mhz 3m bit 4m bit 1.2 v/3.3 v 136-ball csp-bga bc-136-2 adsp-21364bbcz-1aa 2 C40 c to +85 c 333 mhz 3m bit 4m bit 1.2 v/3.3 v 136-ball csp-bga bc-136-2 adsp-21364wbbcz-1a 2 C40 c to +85 c 333 mhz 3m bit 4m bit 1.2 v/3.3 v 136-ball csp-bga bc-136-2 asdp-21365kbc-1aa 3 3 available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. fo r a complete list, visit our website at www.analog.com/sharc. 0 c to +70 c 333 mhz 3m bit 4m bit 1.2 v/3.3 v 136-ball csp-bga bc-136-2 asdp-21365kbcz-1aa 2, 3 0 c to +70 c 333 mhz 3m bit 4m bit 1.2 v/3.3 v 136-ball csp-bga bc-136-2 asdp-21365bbc-1aa 3 C40 c to +85 c 333 mhz 3m bit 4m bit 1.2 v/3.3 v 136-ball csp-bga bc-136-2 asdp-21365bbcz-1aa 2, 3 C40 c to +85 c 333 mhz 3m bit 4m bit 1.2 v/3.3 v 136-ball csp-bga bc-136-2 asdp-21365wbbcz-1a 2, 3 C40 c to +85 c 333 mhz 3m bit 4m bit 1.2 v/3.3 v 136-ball csp-bga bc-136-2 adsp-21366kbc-1aa 3 0 c to +70 c 333 mhz 3m bit 4m bit 1.2 v/3.3 v 136-ball csp-bga bc-136-2 adsp-21366kbcz-1aa 2, 3 0 c to +70 c 333 mhz 3m bit 4m bit 1.2 v/3.3 v 136-ball csp-bga bc-136-2 adsp-21366bbc-1aa 3 C40 c to +85 c 333 mhz 3m bit 4m bit 1.2 v/3.3 v 136-ball csp-bga bc-136-2 adsp-21366bbcz-1aa 2, 3 C40 c to +85 c 333 mhz 3m bit 4m bit 1.2 v/3.3 v 136-ball csp-bga bc-136-2 adsp-21366wbbcz-1a 2, 3 C40 c to +85 c 333 mhz 3m bit 4m bit 1.2 v/3.3 v 136-ball csp-bga bc-136-2

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